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M41ST84Y M41ST84W
5.0 or 3.0V, 512 bit (64 x 8) SERIAL RTC with SUPERVISORY FUNCTIONS
FEATURES SUMMARY s 5.0 OR 3.0V OPERATING VOLTAGE
s
Figure 1. 16-pin SOIC Package
SERIAL INTERFACE SUPPORTS I2C BUS (400 KHz) OPTIMIZED FOR MINIMAL INTERCONNECT TO MCU 2.5 TO 5.5V OSCILLATOR OPERATING VOLTAGE AUTOMATIC SWITCH-OVER and DESELECT CIRCUITRY CHOICE OF POWER-FAIL DESELECT VOLTAGES: - M41ST84Y: VCC = 4.5 to 5.5V; 4.20V VPFD 4.50V - M41ST84W: VCC = 2.7 to 3.6V; 2.55V VPFD 2.70V 1.25V REFERENCE (for PFI/PFO) COUNTERS FOR TENTHS/HUNDREDTHS OF SECONDS, SECONDS, MINUTES, HOURS, DAY, DATE, MONTH, YEAR, and CENTURY 44 BYTES OF GENERAL PURPOSE RAM PROGRAMMABLE ALARM and INTERRUPT FUNCTION (VALID EVEN DURING BATTERY BACK-UP MODE) WATCHDOG TIMER MICROPROCESSOR POWER-ON RESET BATTERY LOW FLAG ULTRA-LOW BATTERY SUPPLY CURRENT OF 500 nA (max) OPTIONAL PACKAGING INCLUDES A 28LEAD SOIC and SNAPHAT(R) TOP (to be ordered separately) SNAPHAT PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP, WHICH CONTAINS THE BATTERY and CRYSTAL
28 1
s
16 1
s
SO16 (MQ)
s
s
Figure 2. 28-pin SOIC Package*
SNAPHAT (SH) Battery & Crystal
s s
s s
SOH28 (MH)
s s s s
s
s
* Contact Local Sales Office
June 2003
Rev. 4.0
1/31
M41ST84Y, M41ST84W
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. 16-pin SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 5. 28-pin SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 7. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 8. AC Testing Input/Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Crystal Electrical Characteristics (Externally Supplied) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 10. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 11. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 7. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 12. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 13. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 14. Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 15. WRITE Mode Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 16. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 8. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TIMEKEEPER(R) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 9. TIMEKEEPER(R) Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 17. Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 10. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 18. Back-Up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 11. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reset Input (RSTIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 19. RSTIN Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power-fail INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 tREC Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 13. tREC Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 14. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 20. Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 21. Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 20. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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M41ST84Y, M41ST84W
SUMMARY DESCRIPTION The M41ST84Y/W Serial supervisory TIMEKEEPER (R) SRAM is a low power 512-bit static CMOS SRAM organized as 64 words by 8 bits. A built-in 32.768 kHz oscillator (external crystal controlled) and 8 bytes of the SRAM (see Table 9, page 16) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 12 bytes of RAM provide status/control of Alarm, Watchdog and Square Wave functions. Addresses and data are transferred serially via a two line, bi-directional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41ST84Y/W has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the SRAM and clock operations can be supplied by a small lithium button-cell supply when a power failure occurs. Functions available to the user include a non-volatile, time-of-day clock/calendar, Alarm interrupts, Watchdog Timer and programmable Square Wave output. Other features include a Power-On Reset as well as an additional input (RSTIN) which can also generate an output Reset (RST). The eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 Figure 3. Logic Diagram
VCC VBAT
(1)
hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. The M41ST84Y/W is supplied in a 28-lead SOIC SNAPHAT(R) package (which integrates both crystal and battery in a single SNAPHAT top) or a 16pin SOIC. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery/crystal package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is also keyed to prevent reverse insertion. The 28-pin SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is "M4TXX-BR12SH" (see Table 20, page 29). Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
Table 1. Signal Names
XI (1) XO (1) Oscillator Input Oscillator Output Interrupt/Frequency Test/Out Output (Open Drain) Power Fail Input Power Fail Output Reset Output (Open Drain) Reset Input Serial Clock Input Serial Data Input/Output Square Wave Output Watchdog Input Supply Voltage Battery Supply Voltage Ground
XI XO
(1)
IRQ/FT/OUT PFI
(1)
RST
PFO
SCL SDA RSTIN WDI PFI M41ST84Y M41ST84W
IRQ/FT/OUT SQW PFO
RST RSTIN SCL SDA SQW WDI VCC VBAT (1)
VSS
Note: 1. For SO16 package only.
AI03677
VSS
Note: 1. For SO16 package only.
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Figure 4. 16-pin SOIC Connections Figure 5. 28-pin SOIC Connections
SQW NC NC NC NC NC NC WDI RSTIN NC NC NC PFO VSS 1 28 27 2 26 3 25 4 24 5 23 6 7 M41ST84Y 22 8 M41ST84W 21 20 9 19 10 18 11 17 12 16 13 15 14
AI03679
XI XO RST WDI RSTIN PFO VBAT VSS
1 16 15 2 3 14 4 M41ST84Y 13 5 M41ST84W 12 6 11 7 10 9 8
AI03678
VCC NC IRQ/FT/OUT NC PFI SQW SCL SDA
VCC NC IRQ/FT/OUT NC NC NC PFI NC SCL NC RST NC SDA NC
Figure 6. Block Diagram
REAL TIME CLOCK CALENDAR SDA I2C INTERFACE SCL 44 BYTES USER RAM RTC w/ALARM & CALIBRATION WATCHDOG SQUARE WAVE AF WDF IRQ/FT/OUT(1)
Crystal
32KHz OSCILLATOR
SQW
WDI VCC
POWER
VBAT VBL= 2.5V COMPARE BL
VSO = 2.5V
COMPARE
VPFD = 4.4V RSTIN
COMPARE
POR RST(1)
(2.65V for ST84W)
PFI COMPARE 1.25V PFO
(Internal)
AI03931
Note: 1. Open drain output
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M41ST84Y, M41ST84W
Figure 7. Hardware Hookup
Regulator Unregulated Voltage VIN VCC M41ST84Y/W VCC IRQ/FT/OUT To INT
From MCU
SCL WDI RSTIN
SDA RST SQW To RST To LED Display
R1 PFI R2 VSS PFO To NMI
AI03680
MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 2. Absolute Maximum Ratings
Symbol TSTG TSLD (1) VIO VCC IO PD Parameter Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds Input or Output Voltages
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Value SNAPHAT(R) SOIC -40 to 85 -55 to 125 260 -0.3 to VCC + 0.3 M41ST84Y -0.3 to 7.0 -0.3 to 4.6 20 1
Unit C C C V V V mA W
Supply Voltage M41ST84W Output Current Power Dissipation
Note: 1. Reflow at peak temperature of 215C to 225C for < 60 seconds (total thermal budget not to exceed 180C for between 90 to 120 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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M41ST84Y, M41ST84W
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the MeasureTable 3. DC and AC Measurement Conditions
Parameter VCC Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
M41ST84Y 4.5 to 5.5V -40 to 85C 100pF 50ns 0.2 to 0.8VCC 0.3 to 0.7VCC
M41ST84W 2.7 to 3.6V -40 to 85C 50pF 50ns 0.2 to 0.8VCC 0.3 to 0.7VCC
Figure 8. AC Testing Input/Output Waveforms
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Note: 50pF for M41ST84W.
Table 4. Capacitance
Symbol CIN CIO(3) tLP Input Capacitance Input / Output Capacitance Low-pass filter input time constant (SDA and SCL) Parameter(1,2) Min Max 7 10 50 Unit pF pF ns
Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
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Table 5. DC Characteristics
Sym Parameter Battery Current OSC ON Battery Current OSC OFF Supply Current Supply Current (Standby) Input Leakage Current ILI(2) Input Leakage Current (PFI) Output Leakage Current Input High Voltage Input Low Voltage Battery Voltage Output High Voltage(4) Output Low Voltage VOL Output Low Voltage (Open Drain)(5) Power Fail Deselect PFI Input Threshold PFI Hysteresis VSO
Note: 1. 2. 3. 4. 5.
Test Condition(1) TA = 25C, VCC = 0V, VBAT = 3V f = 400kHz SCL, SDA = VCC - 0.3V 0V VIN VCC
M41ST84Y Min Typ 400 50 1.4 1 1 -25 2 25 1 0.7VCC -0.3 2.5 3.0 VCC + 0.3 0.3VCC 3.5(6) 0.7VCC -0.3 2.5 2.4 0.4 0.4 4.20 4.40 1.250 20 2.5 4.50 1.275 70 2.55 1.225 -25 Max 500 Min
M41ST84W Unit Typ 400 50 0.75 0.50 1 2 25 1 VCC + 0.3 0.3VCC 3.0 3.5(6) Max 500 nA nA mA mA A nA A V V V V 0.4 0.4 2.60 1.250 20 2.5 2.70 1.275 70 V V V V mV V
IBAT
ICC1 ICC2
ILO(3) VIH VIL VBAT VOH
0V VOUT VCC
IOH = -1.0mA IOL = 3.0mA IOL = 10mA
2.4
VPFD VPFI
VCC = 5V(Y) VCC = 3V(V) PFI Rising
1.225
Battery Back-up Switchover
Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.7 to 3.6V or 4.5 to 5.5V (except where noted). RSTIN internally pulled-up to VCC through 100K resistor. WDI internally pulled-down to VSS through 100K resistor. Outputs deselected. For PFO and SQW pins (CMOS). For IRQ/FT/OUT, RST pins (Open Drain): if pulled-up to supply other than VCC, this supply must be equal to, or less than 3.0V when VCC = 0V (during battery back-up mode). 6. For rechargeable back-up, VBAT (max) may be considered VCC.
Table 6. Crystal Electrical Characteristics (Externally Supplied)
Symbol f0 RS CL Parameter(1,2) Resonant Frequency Series Resistance Load Capacitance 12.5 Typ 32.768 50 Min Max Unit kHz k pF
Note: 1. Load capacitors are integrated within the M41ST84Y/W. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 2. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type.
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M41ST84Y, M41ST84W
OPERATING MODES The M41ST84Y/W clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 64 bytes contained in the device can then be accessed sequentially in the following order: 1. Tenths/Hundredths of a Second Register 2. Seconds Register 3. Minutes Register 4. Century/Hours Register 5. Day Register 6. Date Register 7. Month Register 8. Year Register 9. Control Register 10. Watchdog Register 11 - 16. Alarm Registers 17 - 19. Reserved 20. Square Wave Register 21 - 64. User RAM The M41ST84Y/W clock continually monitors VCC for an out-of tolerance condition. Should VCC fall below VPFD, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. When VCC falls below VSO, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. As system power returns and VCC rises above VSO , the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD(min) plus tREC (min). For more information on Battery Storage Life refer to Application Note AN1012. 2-Wire Bus Characteristics The bus is intended for communication between different ICs. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is High.
- Changes in the data line, while the clock line is High, will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy. Both data and clock lines remain High. Start data transfer. A change in the state of the data line, from High to Low, while the clock is High, defines the START condition. Stop data transfer. A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition. Data Valid. The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter", the receiving device that gets the message is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves". Acknowledge. Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition.
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M41ST84Y, M41ST84W
Figure 9. Serial Bus Data Transfer Sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
Figure 10. Acknowledgement Sequence
START SCLK FROM MASTER 1 2 8 CLOCK PULSE FOR ACKNOWLEDGEMENT 9
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
Figure 11. Bus Timing Requirements Sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
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M41ST84Y, M41ST84W
Table 7. AC Characteristics
Symbol fSCL tBUF tF tHD:DAT(2) tHD:STA tHIGH tLOW tR tSU:DAT tSU:STA tSU:STO SCL Clock Frequency Time the bus must be free before a new transmission can start SDA and SCL Fall Time Data Hold Time START Condition Hold Time (after this period the first clock pulse is generated) Clock High Period Clock Low Period SDA and SCL Rise Time Data Setup Time START Condition Setup Time (only relevant for a repeated start condition) STOP Condition Setup Time 100 600 600 0 600 600 1.3 300 Parameter(1) Min 0 1.3 300 Max 400 Unit kHz s ns s ns ns s ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.7 to 3.6V or 4.5 to 5.5V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
11/31
M41ST84Y, M41ST84W
READ Mode In this mode the master reads the M41ST84Y/W slave after setting the slave address (see Figure 12, page 12). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge Bit, the word address `An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ Mode Control Bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge Clock. The M41ST84Y/W slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to "An+2." Figure 12. Slave Address Location
R/W
This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter (see Figure 13, page 12). The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer increments to a non-clock or RAM address. Note: This is true both in READ Mode and WRITE Mode. An alternate READ Mode may also be implemented whereby the master reads the M41ST84Y/W slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 14, page 13).
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
Figure 13. READ Mode Sequence
START START R/W
BUS ACTIVITY: MASTER
SDA LINE
S
WORD ADDRESS (An)
S
R/W
DATA n
DATA n+1
ACK
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS
DATA n+X
P
AI00899
12/31
NO ACK
STOP
ACK
M41ST84Y, M41ST84W
Figure 14. Alternate READ Mode Sequence
START STOP DATA n ACK ACK DATA n+1 ACK ACK DATA n+X P NO ACK
AI00895
BUS ACTIVITY: MASTER SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
WRITE Mode In this mode the master transmitter transmits to the M41ST84Y/W slave receiver. Bus protocol is shown in Figure 15, page 13. Following the START condition and slave address, a logic '0' (R/ W=0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is Figure 15. WRITE Mode Sequence
START
BUS ACTIVITY: MASTER
R/W
strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge clock. The M41ST84Y/W slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address (see Figure 12, page 12) and again after it has received the word address and each data byte.
R/W
SDA LINE
S
WORD ADDRESS (An)
DATA n
DATA n+1
DATA n+X
P
ACK
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00591
ACK
STOP
13/31
M41ST84Y, M41ST84W
Data Retention Mode With valid VCC applied, the M41ST84Y/W can be accessed as described above with READ or WRITE cycles. Should the supply voltage decay, the M41ST84Y/W will automatically deselect, write protecting itself when VCC falls between VPFD(max) and VPFD(min). This is accomplished by internally inhibiting access to the clock registers. At this time, the Reset pin (RST) is driven active and will remain active until VCC returns to nominal levels. When VCC falls below the Battery Back-up Switchover Voltage (VSO), power input is switched from the VCC pin to the SNAPHAT(R) (or Figure 16. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tDR PFO tRB tREC tR
external) battery, and the clock registers and SRAM are maintained from the attached battery supply. All outputs become high impedance. On power up, when VCC returns to a nominal value, write protection continues for tREC. The RST signal also remains active during this time (see Figure 16, page 14). For a further more detailed review of lifetime calculations, please see Application Note AN1012.
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
RST HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI03681
Table 8. Power Down/Up AC Characteristics
Symbol tF(2) tFB(3) tPFD tR tRB tREC(4) tDR
(5)
Parameter(1) VPFD(max) to VPFD(min) VCC Fall Time VPFD(min) to VSS VCC Fall Time PFI to PFO Propagation Delay VPFD(min) to VPFD(max) VCC Rise Time VSS to VPFD(min) VCC Rise Time Power up Deselect Time Expected Data Retention Time
Min 300 10
Typ
Max
Unit s s
15 10 1 40 10
25
s s s
200
ms YEARS
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.7 to 3.6V or 4.5 to 5.5V (except where noted). 2. VPFD(max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD(min). 3. VPFD(min) to VSS fall time of less than tFB may cause corruption of RAM data. 4. Programmable (see Table 13, page 23) 5. At 25C (when using SOH28 + M4T28-BR12SH SNAPHAT top); VCC = 0V.
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M41ST84Y, M41ST84W
CLOCK OPERATION The eight byte clock register (see Table 9, page 16) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained within the first four registers. Note: A WRITE to any clock register will result in the Tenths/Hundredths of Seconds being reset to "00," and Tenths/Hundredths of Seconds cannot be written to any value other than "00." Bits D6 and D7 of Clock Register 03h (Century/ Hours Register) contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 04h contain the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month and Years. The ninth clock register is the Control Register (this is described in the Clock Calibration section). Bit D7 of Register 01h contains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second. The eight clock registers may be read one byte at a time, or in a sequential block. The Control Register (Address location 08h) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the
eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ. Note: When a power failure occurs, the Halt Update Bit (HT) will automatically be set to a '1.' This will prevent the clock from updating the TIMEKEEPER(R) registers, and will allow the user to read the exact time of the power-down event. Resetting the HT Bit to a '0' will allow the clock to update the TIMEKEEPER registers with the current time. TIMEKEEPER (R) Registers The M41ST84Y/W offers 12 additional internal registers which contain the Alarm, Watchdog, Flag, Square Wave and Control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer increments to a non-clock or RAM address. TIMEKEEPER and Alarm Registers store data in BCD. Control, Watchdog and Square Wave Registers store data in Binary Format.
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M41ST84Y, M41ST84W
Table 9. TIMEKEEPER(R) Register Map
Data Address D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h OUT WDS AFE RPT4 RPT3 RPT2 RPT1 WDF 0 0 0 RS3 ST 0 CEB TR 0 0 CB 0 0 0 0 D6 D5 D4 D3 D2 D1 D0 0.1 Seconds 10 Seconds 10 Minutes 10 Hours 0 10 Date 10M 0 0 0.01 Seconds Seconds Minutes Hours (24 Hour Format) Day of Week Date: Day of Month Month Year Calibration BMB2 Al 10M BMB1 BMB0 RB1 RB0 Function/Range BCD Format Seconds Seconds Minutes Century/Hours Day Date Month Year Control Watchdog Al Month Al Date Al Hour Al Min Al Sec 0 0 0 0 0 Flags Reserved Reserved Reserved SQW 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 0-1/00-23 01-7 01-31 01-12 00-99
10 Years FT BMB4 SQWE RPT5 HT S BMB3 ABE
Alarm Month Alarm Date Alarm Hour Alarm Minutes Alarm Seconds 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AI 10 Date AI 10 Hour
Alarm 10 Minutes Alarm 10 Seconds AF 0 0 0 RS2 0 0 0 0 RS1 BL 0 0 0 RS0
Keys: S = Sign Bit FT = Frequency Test Bit ST = Stop Bit 0 = Must be set to zero BL = Battery Low Flag (Read only) BMB0-BMB4 = Watchdog Multiplier Bits CEB = Century Enable Bit CB = Century Bit OUT = Output level AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits WDS = Watchdog Steering Bit ABE = Alarm in Battery Back-Up Mode Enable Bit RPT1-RPT5 = Alarm Repeat Mode Bits WDF = Watchdog flag (Read only) AF = Alarm flag (Read only) SQWE = Square Wave Enable RS0-RS3 = SQW Frequency HT = Halt Update Bit TR = tREC Bit
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M41ST84Y, M41ST84W
Calibrating the Clock The M41ST84Y/W is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed +/-35 PPM (parts per million) oscillator frequency error at 25oC, which equates to about +/-1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than +1/-2 PPM at 25C. The oscillation rate of crystals changes with temperature (see Figure 20, page 24). Therefore, the M41ST84Y/W design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 21, page 24. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bits occupy the five lower order bits (D4-D0) in the Control Register (08h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 PPM of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month
which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41ST84Y/W may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Application Note AN934: TIMEKEEPER CALIBRATION. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT/OUT pin. The pin will toggle at 512Hz, when the Stop Bit (ST, D7 of 01h) is '0,' the Frequency Test Bit (FT, D6 of 08h) is '1,' the Alarm Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the Watchdog Steering Bit (WDS, D7 of 09h) is '1' or the Watchdog Register (09h = 0) is reset. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 PPM oscillator frequency error, requiring a -10 (XX001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. The IRQ/FT/OUT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500 to 10k resistor is recommended in order to control the rise time. The FT Bit is cleared on power-down.
17/31
M41ST84Y, M41ST84W
Setting Alarm Clock Registers Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. It can also be programmed to go off while the M41ST84Y/W is in the battery back-up to serve as a system wake-up call. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 10, page 18 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT/OUT pin. Note: If the address pointer is allowed to increment to the Flag Register address, an alarm condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a different adFigure 17. Alarm Interrupt Reset Waveform
dress. It should also be noted that if the last address written is the "Alarm Seconds," the address pointer will increment to the Flag address, causing this situation to occur. The IRQ/FT/OUT output is cleared by a READ to the Flags Register as shown in Figure 17. A subsequent READ of the Flags Register is necessary to see that the value of the Alarm Flag has been reset to '0.' The IRQ/FT/OUT pin can also be activated in the battery back-up mode. The IRQ/FT/OUT will go low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set. The ABE and AFE Bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the Flag Register at system boot-up to determine if an alarm was generated while the M41ST84Y/W was in the deselect mode during power-up. Figure 18, page 19 illustrates the back-up mode alarm timing.
0Eh
0Fh
10h
ACTIVE FLAG
IRQ/FT/OUT
HIGH-Z
AI03664
Table 10. Alarm Repeat Modes
RPT5 1 1 1 1 1 0 RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm Setting Once per Second Once per Minute Once per Hour Once per Day Once per Month Once per Year
18/31
M41ST84Y, M41ST84W
Figure 18. Back-Up Mode Alarm Waveform
VCC VPFD
VSO tREC ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/FT/OUT HIGH-Z HIGH-Z
AI03920
Watchdog Timer The watchdog timer can be used to detect an outof-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the Watchdog Register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3*1, or 3 seconds). Note: Accuracy of timer is within the selected resolution. If the processor does not reset the timer within the specified period, the M41ST84Y/W sets the WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS). When set to a '0,' the watchdog will activate the IRQ/FT/OUT pin when timed-out. When WDS is set to a '1,' the watchdog will output a negative pulse on the RST pin for tREC. The Watchdog register, FT, AFE, ABE and SQWE Bits will reset to a '0' at the end of a Watchdog time-out when the WDS Bit is set to a '1.'
The watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high) can be applied to the Watchdog Input pin (WDI) or 2) the microprocessor can perform a WRITE of the Watchdog Register. The time-out period then starts over. Note: The WDI pin should be tied to VSS if not used. In order to perform a software reset of the watchdog timer, the original time-out period can be written into the Watchdog Register, effectively restarting the count-down cycle. Should the watchdog timer time-out, and the WDS Bit is programmed to output an interrupt, a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ/FT/OUT pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the Flags Register will reset the Watchdog Flag (Bit D7; Register 0Fh). The watchdog function is automatically disabled upon power-up and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ/FT/OUT pin and the Frequency Test (FT) function is activated, the watchdog function prevails and the Frequency Test function is denied.
19/31
M41ST84Y, M41ST84W
Square Wave Output The M41ST84Y/W offers the user a programmable square wave function which is output on the SQW pin. The RS3-RS0 Bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 11. Once the selection Table 11. Square Wave Output Frequency
Square Wave Bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Square Wave Frequency None 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1 Units - kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the Square Wave Enable Bit (SQWE) located in Register 0Ah.
20/31
M41ST84Y, M41ST84W
Power-on Reset The M41ST84Y/W continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC passes VPFD(max). The RST pin is an open drain output and an appropriate pull-up resistor should be chosen to control rise time. Reset Input (RSTIN) The M41ST84Y/W provides an independent input which can generate an output reset. The duration and function of this reset is identical to a reset generated by a power cycle. Table 12, page 21 and Figure 19, page 21 illustrate the AC reset characteristics of this function. Pulses shorter than tRLRH will not generate a reset condition. RSTIN is internally pulled up to VCC through a 100k resistor.
Figure 19. RSTIN Timing Waveform
RSTIN tRLRH
RST
(1)
tRHRSH
AI03682
Note: With pull-up resistor
Table 12. Reset AC Characteristics
Symbol tRLRH(2) tRHRSH(3) Parameter(1) RSTIN Low to RSTIN High RSTIN High to RST High Min 200 40 200 Max Unit ns ms
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.7 to 3.6V or 4.5 to 5.5V (except where noted). 2. Pulse width less than 50ns will result in no RESET (for noise immunity). 3. Programmable (see Table 14, page 23)
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M41ST84Y, M41ST84W
Power-fail INPUT/OUTPUT The Power-Fail Input (PFI) is compared to an internal reference voltage (1.25V). If PFI is less than the power-fail threshold (VPFI), the Power-Fail Output (PFO) will go low. This function is intended for use as an under-voltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure 7, page 6) to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the M41ST84Y/W or the microprocessor drops below the minimum operating voltage. During battery back-up, the power-fail comparator turns off and PFO goes (or remains) low. This occurs after VCC drops below VPFD(min). When power returns, PFO is forced high, irrespective of VPFI for the write protect time (tREC), which is the time from VPFD(max) until the inputs are recognized. At the end of this time, the power-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. Century Bit Bits D7 and D6 of Clock Register 03h contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a "1" will cause CB to toggle, either from a "0" to "1" or from "1" to "0" at the turn of the century (depending upon its initial state). If CEB is set to a "0", CB will not toggle. Output Driver Pin When the FT Bit, AFE Bit and watchdog register are not set, the IRQ/FT/OUT pin becomes an output driver that reflects the contents of D7 of the Control Register. In other words, when D7 (OUT Bit) and D6 (FT Bit) of address location 08h are a '0,' then the IRQ/FT/OUT pin will be driven low. Note: The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor. Battery Low Warning The M41ST84Y/W automatically performs battery voltage monitoring upon power-up and at factoryprogrammed time intervals of approximately 24 hours. The Battery Low (BL) Bit, Bit D4 of Flags Register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5V. The
BL Bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. The SNAPHAT top may be replaced while VCC is applied to the device. Note: This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is disconnected. The M41ST84Y/W only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. tREC Bit Bit D7 of Clock Register 04h contains the tREC Bit (TR). tREC refers to the automatic continuation of the deselect time after VCC reaches VPFD. This allows for a voltage setting time before WRITEs may again be performed to the device after a powerdown condition. The tREC Bit will allow the user to set the length of this deselect time as defined by Table 13, page 23. Initial Power-on Defaults Upon initial application of power to the device, the following register bits are set to a '0' state: Watchdog Register, TR, FT, AFE, ABE, and SQWE. The following bits are set to a '1' state: ST, OUT, and HT (see Table 14, page 23).
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M41ST84Y, M41ST84W
Table 13. t REC Definitions
tREC Bit (TR) 0 0 1
Note: 1. Default Setting
STOP Bit (ST) Min 0 1 X 96 40 50
tREC Time Max 98 200(1) 2000
Units ms ms s
Table 14. Default Values
Condition Initial Power-up (Battery Attach for SNAPHAT)(2) Subsequent Power-up (with battery back-up)(3) TR 0 UC ST 1 UC HT 1 1 Out 1 UC FT 0 0 AFE 0 0 ABE 0 0 SQWE 0 0 WATCHDOG Register(1) 0 0
Note: 1. WDS, BMB0-BMB4, RB0, RB1. 2. State of other control bits undefined. 3. UC = Unchanged
23/31
M41ST84Y, M41ST84W
Figure 20. Crystal Accuracy Across Temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = -0.038 ppm (T - T )2 10% 0 F C2 T0 = 25 C
Temperature C
AI00999
Figure 21. Clock Calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
24/31
M41ST84Y, M41ST84W
PACKAGE MECHANICAL INFORMATION Figure 22. SO16 - 16-lead Plastic Small Outline, Package Outline
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Note: Drawing is not to scale.
Table 15. SO16 - 16-lead Plastic Small Outline, Package Mechanical Data
mm Symbol Typ. A A1 A2 B C D E e H L a N CP 1.27 0.35 0.19 9.80 3.80 - 5.80 0.40 0 16 0.10 0.10 Min. Max. 1.75 0.25 1.60 0.46 0.25 10.00 4.00 - 6.20 1.27 8 0.050 0.014 0.007 0.386 0.150 - 0.228 0.016 0 16 0.004 0.004 Typ. Min. Max. 0.069 0.010 0.063 0.018 0.010 0.394 0.158 - 0.244 0.050 8 inches
25/31
M41ST84Y, M41ST84W
Figure 23. SOH28 - 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Note: Drawing is not to scale.
Table 16. SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C D E e eB H L N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inches
26/31
M41ST84Y, M41ST84W
Figure 24. SH - 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note: Drawing is not to scale.
Table 17. SH - 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data
millimeters Symbol Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.0181 0.8350 0.5598 0.6122 0.1260 0.0799 0.2650 0.2551 Typ Min Max 0.3850 0.2850 0.2752 0.0150 0.0220 0.8598 0.5902 0.6280 0.1421 0.0902 inches
27/31
M41ST84Y, M41ST84W
Figure 25. SH - 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note: Drawing is not to scale.
Table 18. SH - 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data
millimeters Symbol Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 10.54 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.0181 0.8350 0.5598 0.6122 0.1260 0.0799 0.2650 0.2551 Typ Min Max 0.4150 0.2850 0.2752 0.0150 0.0220 0.8598 0.5902 0.6280 0.1421 0.0902 inches
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M41ST84Y, M41ST84W
PART NUMBERING Table 19. Ordering Information Scheme
Example: M41ST 84Y MQ 6 TR
Device Type M41ST
Supply Voltage and Write Protect Voltage 84Y = VCC = 4.5 to 5.5V; 4.20V VPFD 4.50V 84W = VCC = 2.7 to 3.6V; 2.55V VPFD 2.70V
Package MQ = SO16 MH(1,2) = SOH28
Temperature Range 6 = -40 to 85C
Shipping Method for SOIC blank = Tubes TR = Tape & Reel
Note: 1. The 28-pin SOIC package (SOH28) requires the battery/crystal package (SNAPHAT(R)) which is ordered separately under the part number "M4TXX-BR12SHX" in plastic tube or "M4TXX-BR12SHXTR" in Tape & Reel form. 2. Contact Local Sales Office Caution: Do not place the SNAPHAT battery package "M4TXX-BR12SH" in conductive foam as it will drain the lithium button-cell battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 20. SNAPHAT Battery Table
Part Number M4T28-BR12SH M4T32-BR12SH Description Lithium Battery (48mAh) and Crystal SNAPHAT Lithium Battery (120mAh) and Crystal SNAPHAT Package SH SH
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M41ST84Y, M41ST84W
REVISION HISTORY Table 21. Document Revision History
Date August 2000 24-Aug-00 08-Sep-00 18-Dec-00 Rev. # 1.0 1.2 1.3 2.0 First Issue Block Diagram added (Figure 6) SO16 package measures change Reformatted, TOC added, and PFI Input Leakage Current added (Table 5) Addition of tREC information, table changed, one added (Tables 9, 13); changes to PFI/PFO graphic (see Figure 6); change to DC and AC Characteristics, Order Information (Tables 5, 7, 19); note added to "Setting Alarm Clock Registers" section; added temp./voltage info. to tables (Table 4, 5, 6, 7, 8); addition of Default Values (Table 14); textual improvements Special note added in "Clock Operation" section (page 15) Change in Product Maturity Improve text for "Setting the Alarm Clock" section Change VPFD values in document DC Characteristics VBAT changed; PFI Hysteresis (PFI Rising) spec. added; and Crystal Electrical Characteristics Series Resistance spec. changed (Tables 5, 6) Change READ/WRITE Mode Sequence drawings (Figure 13, 15); change in VPFD lower limit for 5V (M41ST84Y) part only (Table 5, 19) Change Series Resistance (Table 6) Change tREC Definition (Table 13); modify reflow time and temperature footnote (Table 2) Modify DC and Crystal Electrical Characteristics footnotes, Default Values (Tables 5, 6, 14) Add marketing status (Figure 2; Table 19) New Si changes (Table 8, 12, 13, 14) Revision Details
18-Jun-01
2.1
25-Jun-01 26-Jul-01 07-Aug-01 20-Aug-01 06-Sep-01 03-Dec-01 14-Jan-02 01-May-02 03-Jul-02 01-Aug-02 16-Jun-03
2.2 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 4.0
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M41ST84Y, M41ST84W
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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